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Interrupts, the role of interrupts and Interrupt Service Routines (ISR), role within the Fetch-Decode-Execute Cycle

Definition - Hardware and software indicating an event needs immediate attention. They 'interrupt' what the processor is doing

Objectives

Optimise use of CPU time

  • Enable multi-tasking
    • Enables scheduling - e.g. an interrupt could indicate end of a time slide
  • Enables real-time OS
    • High priority events can be dealt with quickly
  • Minimises latency
    • Keypress given high priority to keep system responsive
  • Enables applications to interface with devices/request system services
    • e.g. request connection to device
  • Negates the need for polling devices
    • e.g. polling keyboard to see if a key is pressed is not needed - keyboard integrates an interrupt

Sources

Hardware

  • Keypress
  • Mouse Movement
  • Temperature alert

Hardware interrupts are asynchronous, meaning they can occur in the middle of executing other code. They are on a physical electronic channel connected to the CPU, and are known as interrupt requests (IRQs)

Software

Caused by processes, such as ALU errors, division by zero exception etc.

System Calls

  • Process Control (termination, wait, load execute)
  • File Management (open, close, read, write)
  • Device Management (request connection, release connection)
  • Information Management (get/set time)
  • Communication Management (request connection, transfer status)

What Happens?

Sequence of Events

  • Interrupt Signal is Sent
  • Processor Suspends Current Process
    1. Saves state of CPU registers (could be stored to stack - LIFO data structure)
    2. Executes the ISR (interrupt service routine)
    3. ISR finds the code to handle the interrupt (each interrupt has its own handler)
    4. CPU runs the handler (typically as a thread, 1 per interrupt)
    5. The state of the previous process is restored from the stack
    6. The CPU resumes what it was doing
  • UNLESS a higher priority interrupt arrives - current handler is suspended

Priorities

Interrupt priority level (IPL) is indicated by a bitmask or hardware register. Priorities aim to minimise latency by prioritising certain tasks, such as power failure, clock interrupts, and IO devices such as keyboards, screens and hard drives. Lower level priorities such as rescheduling processes and returning data from IO devices to applications are bypassed by higher level priorities. The actual priority depends on the OS.